1. Field of the Invention:
The present invention relates generally to a system and method for reducing a staircasing effect known as aliasing in polygons drawn on a raster graphics display subsystem. Reducing the staircasing effect by smoothing the edges of the raster polygon is known as antialiasing. More particularly, it relates to such an antialiasing system and method that samples the polygon multiple times per pixel.
2. Description of the Prior Art:
The task of scan-converting a polygon on a raster graphics display subsystem is to determine the coordinates of the pixels which lie inside the polygon on a two-dimensional raster grid. Fully illuminating those pixels inside the line segments comprising the polygon will result in a staircase pattern which approximates the polygon.
Known techniques for antialiasing polygons are both time consuming, computation intensive and would require extensive additional hardware support if implemented in hardware form. Such algorithms serve their intended function well if the raster graphics display subsystem is a high enough performance subsystem. However, for low cost workstation applications, compromises in the raster graphics display processing speed are required in order to be price competitive. The use of reduced instruction set computer (RISC) central processing units (CPUs) in such workstations minimizes the extent of compromise required in processor performance, but the use of traditional antialiasing algorithms would make graphics response in these workstations appear to be sluggish. A need therefore exists for a system and method for antialiasing polygons that is faster and less computation intensive than the traditional techniques.